Bachelor’s degree in Electrical, Electronic or Computer Engineering, a related field or equivalent practical experience.
7 years of experience in the area of ATE test patterns generation, silicon bring up, and diagnosis of mobile chips, processors, and SoC designs.
Experience with standard protocols such as IEEE 1149.1 JTAG, SPI, MDIO, DDR, APB, AXI, etc.
Experience in the area of digital verification and direct experience with industry tools such as Synopsys VCS, Cadence Xcelium for generation of both directed and random tests and using different waveform viewer tools for interactive debug.
Experience in scripting languages (Python, Tcl) and CAD automation tools.
Familiar with different test patterns formats such as STIL, WGL, SVF, VCD, eVCD and ATE fail datalogs.
Strong understanding of System Verilog based verification and generation of both directed and random tests with coverage reporting.
Familiar with UVM based verification methodology along with creating assertions.