Mulya Technologies

Position : Senior Mixed Signal Verification Engineer

 

  • Position Description:
    • To be part of a highly skilled and challenging high speed PHY design team working on the newest technology nodes (12nm and below).
    • Responsible for IP Analog Mix Signal (AMS) behavioral modeling and verification
    • Verilog, Verilog-AMS and real number and MATLAB modeling
    • AMS testplan creation and simulations using co-simulation
    • Work closely with Digital and Analog designers
    • Leading, mentoring and coaching junior team members
    • Equal opportunity position with excellent pay package!
  • SKILLS required:
    • Strong knowledge of Verilog and Verilog-AMS language
    • Experience in behavioral modeling of Analog blocks like PLL, DLL, IO, LDO etc
    • Experience of running and debugging co-simulation involving both analog and digital blocks of PHYs.
    • Basic understanding of Analog macros such as DLL, Bandgap, LDO, PLL, IO pads etc
    • Working knowledge of system modeling in MATLAB
    • Understanding of UVM environment
    • The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.
    • Team leadership experience, including planning and managing tasks is desirable
    • M.S./M.Tech, BS/BE (Electronics)
    • Experience Required : 4+ Years
    • To be part of a highly skilled and challenging high speed PHY design team working on the newest technology nodes (12nm and below).
    • Responsible for overall IP and sub-system verification from test plan creation, UVM development to signoff.
    • Ensure first pass product through multi-dimensional verification coverage including mixed mode verification.
    • Leading, mentoring and coaching junior team members
    • Pair with similar domain specialists across other geographical locations on core technical initiatives
    • Work closely with Digital and Analog designers
    • Equal opportunity position with excellent pay package!
  • SKILLS required:
    • Strong knowledge of DDR/LPDDR JEDEC and DFI protocols
    • Exposure to verification of complex high speed PHY and/or complex AMS IPs
    • Proven track record of building testplan, UVM environment and testbenches
    • Experience with RTL debugging, score boarding and code coverage analysis
    • Sound knowledge of Verilog and System Verilog languages
    • Exposure to modelling and validating complex analog circuits in Verilog and Verilog-A
    • Experience of complex mixed signal design verification using state of the art flows and tools
    • The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.
    • Team leadership experience, including planning and managing tasks is desirable
    • M.S./M.Tech, BS/BE (Electronics)

 

Seniority Level

Mid-Senior level

Industry

  • Semiconductors
  • Consumer Electronics
  • Wireless

Employment Type

Full-time

Job Functions

  • Engineering
  • Design
  • Information Technology

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